The present invention relates generally to digital computing, and more particularly to a tool that takes into account real world constraints when implementing an Engineering Change Order (ECO).
Many microchip designs are crafted in similar processes. At the beginning stage of a typical design process, or “front end”, a logic designer uses a Very High Speed Integrated Circuits (VHSIC) Design Language (VHDL) to generate a behavioral description of the chip or chip element. This behavioral description is abstracted to a fairly high level, such as the bus level, and lower-level constructs, such as pins and individual nets, are not present in the front end behavioral description.
The VHDL behavioral model then proceeds through a behavioral synthesizer to create a Register Transfer Language (“RTL”) VIM (VLSI Integrated Model) netlist. This netlist is less abstract that the VHDL behavioral description, and represents, rather than buses, the individual wires connecting logic boxes. The netlist may be described in a text file that corresponds to the component. The netlist may be a derivative, through additional processing, of a file format that may be as described by Verilog, VHSIC Hardware Design Language (VHDL), among other high-level design languages. Verilog is a trademark of Cadence Design Systems.
The VHDL behavioral description also goes through a logical synthesis, which creates a physical design (“PD”) VIM netlist that is forwarded to the physical designer. The physical designer is involved in the “back end” of the design process, where low-level design decisions are made.
The physical designer typically runs the PD VIM netlist through physical design tools, which places and routes the ultimate, low-level physical components of the chip, such as pins and wires. The design is ultimately sent to a foundry, where the masks for chip processing are finalized. Any changes to the physical chip layout are described in an Engineering Change Order (ECO).
More particularly, in chip design, ECO is the process of inserting a logic change directly into the netlist after it has already been processed by an automatic tool to form the actual layout. Before the chip masks are made, ECOs are usually done to save time, by avoiding the need for full ASIC logic synthesis, technology mapping, place, route, layout extraction, and timing verification.
Functional ECO extraction is indispensable to meet time-to market constraints in today's chip designs. A functional ECO extractor is a program that takes the placed and routed netlist makes changes to it to meet the needed change. There are several different types of ECO extractors and these will generally be called “ECO extractors” herein. Widely used objective functions that a ECO extractor uses include extracting the minimum number of gates and nets for the logical ECO change, stitching the extracted ECO logic to a proper logical point so that the expected functionality with changed logic is obtained, placing the gates to meet the logic of the ECO as well as routing of the ECO nets. Optimization of the ECO logic is typically done on the stitched netlist by the physical synthesis/optimization tool.